Sunday, 04 December 2016

Full Chip, Transistor Level Reliability


Integrating circuit cores together in one chip exposes risks that can fly below the radar of conventional checking methods. After individual cores have been exhaustively simulated, there's still the question of reliability. This is an especially important topic in today's design flows for mixed power and low power. How thoroughly has the circuit been checked before tape-out?

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Take advantage of intelligent detection techniques to help you in your circuit analysis.

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Full Chip, Transistor Level Reliability


We started Insight EDA with one key concept in mind: Checking circuit reliability doesn't have to be difficult. A circuit engineer should be able to bring up a tool, with minimal setup, and get clear results. Tweak the circuit, fix an issue, and submit the updates. - All without waiting on the CAD team for help.

And simple to use doesn't mean simple minded. Checks must be smart enough to know about the ins and outs of real world circuits, automatically. Like novel level shifter topologies, ad-hoc domain isolation, safe vs unsafe power states, and other unexpected situations.

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No Time for ESD?

No Time for ESD?

There's more to ESD than just pad cell design. It's a matter of chip integration. Insight Analyzer chases big picture ESD / EMP risks at the full chip level.
Floating Gates

Floating Gates

Under the wrong conditions, a powered transistor can receive a signal that begins to float. A simulator can fail to warn of cases that float at a “valid” level. Insight Analyzer finds conditional floats by reverse-engineering circuit states, all the way back to the underlying cause.
Domain Crossings

Domain Crossings

Insight Analyzer comprehends full chip power connections at the transistor level. It tracks down problems in power state management of all forms, including voltage mismatch / level shifting, forward biased diodes, and off state isolation.


InsightEDA provides software to fill an unmet need in the Electronics industry.

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