Insight EDA

Analog & Mixed Signal

Many circuit design flaws can slip through design reviews and time domain simulation. Simple topological errors, such as passgates straddling domain crossings. Even complex conditional cases, like hi-impedance floating gates.

...But these defects can be caught by comprehensive Circuit Rule Validation.

Insight Analyzer inspects IC design topology and validates electrical rules in complex, transistor-level circuit designs. Enforcing the reliability of your product includes catching early in the flow, and all the way to tape-out, catching more than with traditional means alone.

What-if Conditional Analysis

Insight Analyzer enforces the success of your IC designs by...

Directly pinpointing circuit reliability risks.
Locating violations that go undetected by time domain simulators.
Indicating the cause of failure instead of the symptom.
Covering all cases with vector-independent, what-if scenario based analysis.

Examples

	Floating Gates Floating MOS gates can arise due to many types of unforeseen conditions...
	Substrate Ties Bulk terminals tied to invalid nets such as inappropriate voltage, soft power, floating, etc.
	Power-Down State Sensitive MOS gate nodes having no valid power-down switches to appropriate rail.
	Power Domain Crossings Risk of floating gates if driver is powered off, or excessive current leakage, or injection of noise into quiet section.
	Missing Level Shifters Gates driven beyond spec, high voltage sneak paths, illegal domain crossings where voltages may match, leaving a violation undetected! Even under-driven receivers, functioning perfectly in simulation but leaking in silicon...