Insight EDA

Custom Digital

Many circuit design flaws can slip through design reviews and time domain simulation. Simple topological errors, such as passgates straddling domain crossings. Even complex conditional cases, like hi-impedance floating gates.

...But these defects can be caught by comprehensive Circuit Rule Validation.

Insight Analyzer inspects IC design topology and validates electrical rules in complex, transistor-level circuit designs. Enforcing the reliability of your product includes catching early in the flow, and all the way to tape-out, catching more than with traditional means alone.

What-if Conditional Analysis

Insight Analyzer enforces the success of your IC designs by...

Directly pinpointing circuit reliability risks.
Locating violations that go undetected by time domain simulators.
Indicating the cause of failure instead of the symptom.
Covering all cases with vector-independent, what-if scenario based analysis.

Examples

	Fanout Optimization From gross over-drive / over-loading, to detailed fanout calculations...
	Long Delay Paths Find signals that may be OK for fanout/loading, but actual parasitic wire delays inject timing violations.
	Keepers Checking keepers against weak drivers, strong leakage, and writeability.
	Domain Crossing: ESD/EMP Checking power islands, power off states, undriven inputs, and EMP risks, all based on your defined power sections.
	Power-Down Blocks Bulk node to switched rail instead of power rail (DC leakage), Switch turns off own control (unrecoverable power-off).