Sunday, 27 May 2018

Create Custom Rule

Floating Node Example

Here’s an example of a circuit check that combines topology with state-based analysis.
The user wants to write a custom check that will look for P + N MOSFET stacks with faulty gate inputs.

The output of such stack can be expected to float, if the gates are not properly configured. This could be called a “broken CMOS” check.
Insight Analyzer has built-in checks for conditional floats, or high-impedance gate nets. But in this example, we look at a simple case and see how a custom rule can be created for a particular situation.



Two similar cases, but one important difference. One of the MOSFET stacks has a possible high-impedance output condition, while the other MOSFET stack will always provide a safe value.



Insight Analyzer has built-in checks for conditional floats. However, there might be a reason for making the specific check described in this application note.
For one thing, this check can quickly scan a library of custom standard cells, and find a float risk far faster than running simulation or ERC at the full chip level.
A major advantage to using the Insight Analyzer for this check is: Insight Analyzer uses a blend of topology plus state-based analysis to:

  • A: Find the topological areas of interest that should be tested. Then
  • B: Accurately test and weed out false positives.

***The methods described in this application note are patent protected by Insight EDA Inc.


Finding Suspects

The first step is to find MOSFET stacks that must be tested. A user may have different requirements in this area, so we will have some general pointers but leave the rest up to the individual user:

  • A static circuit pattern can be defined with a subgraph template.

Insight Analyzer looks at subgraph isomorphism and matches up circuit patterns when a chip netlist is loaded.These are defined in config/SubgraphTemplates.config, or alternate files.
A node can be queried to see if it has NFET and PFET source or drain, and MOSFET gates. This node would be considered as a target to be tested.

  • The command to do this is‘  cdb net ... getPinTypes’.
  • This test can be done within a circuit iterator loop such as ‘cscan nets’.

The result of this step is to find the nets that should be tested.


Test for Conditional Float

After finding a net to test, there are two commands we will use to detect a high-impedance condition in Insight Analyzer:
Constrain the test within the net’s own cell. This will keep the solver from leaving the cell and exploring the rest of the chip for other input conditions. Those input conditions are outside the mission statement of this example.

  • The command is:    ’cdb fg “set ceiling” ...’
  • Test the given net with this command:   ’cdb fg “eqtree hyp … Z”’ The return value is either True or False.

The circuit is explored backward, to find input conditions that will either allow a float (true result), or prevent a float (false result).
Use Tcl expression parsing to resolve the returned outcome and format an appropriate circuit checking report.


One of these cases does have a potential float condition, while the other one is safe. Insight Analyzer is considering all possible state values on the inputs to the MOSFET stacks, and is able to discriminate between the real and false cases.


TCL Example Scripts

Could be found in any standard example working directories. 

InsightEDA provides software to fill an unmet need in the Electronics industry.


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