Sunday, 21 January 2018

Multi Power Domain

Power State Combinations
The Insight Analyzer is state aware. A power state table, such as UPF, may be used for circuit checking. This eliminates false positives where domains track each other, while revealing violations such as forward biased diodes from power-up sequence.

Contention can manifest in many cases beyond just shorted drivers. In fact, contention cases can be much more complex. There might be a pre-charge circuit facing an off state shunt that's actually on. Or a multiplexer with badly constructed controls, resulting in multiple legs on at once. Or a passgate reset that's on at the wrong time. The Insight Analyzer works to reverse-engineer the conditions that cause contention.

Conditional floats
The key word is “conditional”. A MOSFET gate may be properly tied to a driver output, but what if the driver can be turned off? Or the driver is a passgate that leads to nowhere? Or the driver is an amplifier that has its current reference taken away during power down? The Insight Analyzer examines every MOSFET gate node, and works in reverse to discover the conditions that lead to high-impedance states. These conditions may be digital, like off passgates, or analog, like collapsed references.


Toplevel port integrity
Do the circuit's top IO ports meet the boundary specs? Insight Analyzer has two modes of checking circuit IO: Audit mode, listing the actual port directions and associated rails; and ERC mode, enforcing the given specs of voltage level, IO direction, associated rails, power mixture, series passgates, and more.

Domain Isolation
When a block is powered off, its floating outputs may reach unprotected inputs on another block, still powered. Insight Analyzer runs comprehensive checks for these situations and finds various manifestations of:

  • Isolation that crosses domains (produces the desired result, but can float itself)
  • Missing isolation cell
  • Wrong isolation control state (wrong inversion from master control)
  • Missing isolation control

Cross-Domain Level Shifters
An input that is not fully driven may pass simulation, but leak DC current in silicon. This type of circuit fault can be difficult to track down with standard methods, especially if power supplies are variable, or if there is a crossing from a noisy section to a quiet section.

Path Delays
A strong driver in one block runs to a corresponding receiver inside another block. With enough physical separation, such as over chip top, there can be a gross slew rate violation. But in a large netlist with parasitics, it might not be practical to simulate. Insight Analyzer has a module dedicated to this purpose.

Analog / Mixed Signal

Power Down Safety

A power down state brings risk in analog circuits.

When analog sections are selectively powered off, some nodes may not completely reach ground. These indeterminate values can result in random silicon failures. Insight Analyzer finds these nodes and checks for missing bleeder devices.

Further, any nodes that float under such conditions will cause problems at the gates of powered transistors. Insight Analyzer identifies all MOSFET gate nodes, then runs a detailed check of upstream conditions, looking for the possibility of floating gates.

Antenna Diodes
Antenna diodes are placed on critical inputs. If, for example, the circuit's reference node is brought to a more positive value only in exceptional conditions, it may not be detected by simulation. Insight Analyzer has specific checks for these cases.

Custom Digital

Fanout / Loading
Comprehensive analysis is done at the primitive transistor level, looking for fanout values that lie outside an ideal window (min and max). The analysis takes into account geometry variations, passgates in critical path, degradation through stacks and power switches, and parasitic loading.

Beta Ratio
A rule to check beta ratio examines all recognized and unrecognized CMOS structures for sizing conformance.

Keeper circuits are checked both for being too weak and too strong. A weak keeper may not be able to hold its value against strong leakage. A strong keeper may prevent changes by a weak driver.

Latch Writability
If a driver faces a jam latch through a pass gate, there can be a risk that the driver may not be able to write the latch value. The Insight Analyzer considers the whole combination of driver strength plus pass gate geometry plus jam latch strength all at once, to find these risky cases.

Victim / Aggressor / Noise
With extracted parasitics info, the Insight Analyzer finds victims susceptible to noise, such as:

  • Dynamic storage nodes
  • Analog reference nodes
  • Off-state passgates that may suddenly turn on

In a digital circuit, contention can be more complex than shorted drivers. The “shorting” may take place through passgates, reset circuits, badly constructed multiplexers, 3-state enables, and more. In fact, it might not even be simple shorting. Perhaps a dynamic stage has DC paths conducting from power to ground simultaneously.

InsightEDA provides software to fill an unmet need in the Electronics industry.


Quick Links

Social Links