For Mixed Power,
High Reliability Circuits


Full Chip, Transistor Level Reliability

Integrating circuit cores together in one chip exposes risks that can fly below the radar of conventional checking methods. After individual cores have been exhaustively simulated, there's still the question of reliability. This is an especially important topic in today's design flows for mixed power and low power.

Checking circuit reliability doesn't have to be difficult. A circuit engineer should be able to bring up a tool, with minimal setup, and get clear results. Tweak the circuit, fix an issue, and submit the updates. - All without waiting on the CAD team for help.

And simple to use doesn't mean simple minded. Checks must be smart enough to know about the ins and outs of real world circuits, automatically. Like novel level shifter topologies, ad-hoc domain isolation, safe vs unsafe power states, and other unexpected situations.


We're excited to announce the release of Insight Analyzer v5.0.

This major version update of Insight Analyzer has significant updates over prior versions in the v4x series. There are new features, behavior changes, and migration aspects.

  • Re-designed GUI for improved workflow, enhanced detail, and improved status of the internal engine.
  • New "Analog States" method of state-driven checking that combines UPF and testbenches. See our white paper for more details.
  • New example search feature to find relevant examples within a vast library of example projects.
  • Integration with StarvisionPRO, for cross-probing outward from within the Insight GUI.
  • Analog high-impedance cases have been split into their own check, to focus more on this one core area of specialty.
  • Cross Domain high-impedance cases have been split into a dedicated set of checks, separate from the analog cases. Now, the complexities of these cross domain isolation issues can be more extensively checked.

Please see the full release notes here

New developments for leakage detection


Parasitic Leakage

  • Leakage through parasitic body diodes.
  • Bulk is not biased high enough (PMOS) or low enough (NMOS).
  • Long term reliability risk (device degradation over multiple cycles).
  • Short term reliability risk (latch up, damage).
  • Poor power performance (battery leakage).

Analog Gate Leakage

  • Leakage from power supply to ground, through MOSFET stacks.
  • Gate input floating, high impedance state.
  • Low reliability: Improper states, unreliable outcomes, etc.
  • High current drain.

Digital Gate Leakage

  • Category of power management / mismatch issues.
  • Input may be under driven, “missing level shifter”.
  • Input may be floating, high impedance state.
  • Low reliability: Improper states, unreliable outcomes, etc.
  • High current drain.