Full Chip, Transistor Level Reliability
Integrating circuit cores together in one chip exposes risks that can fly below the radar of conventional checking methods. After individual cores have been exhaustively simulated, there's still the question of reliability. This is an especially important topic in today's design flows for mixed power and low power.
Checking circuit reliability doesn't have to be difficult. A circuit engineer should be able to bring up a tool, with minimal setup, and get clear results. Tweak the circuit, fix an issue, and submit the updates. - All without waiting on the CAD team for help.
And simple to use doesn't mean simple minded. Checks must be smart enough to know about the ins and outs of real world circuits, automatically. Like novel level shifter topologies, ad-hoc domain isolation, safe vs unsafe power states, and other unexpected situations.
News
We're excited to announce the release of Insight Analyzer v5.21.
This is an incremental update with bug fixes and usability improvements based on the previous v5.20.
- Extended capabilities in the Power & Boundary editing workspace in the GUI.
- Increased flexibility in making power state definitions, and handling the overlap between different state related checks.
- Float and Contention checks: Numerous extensions to support additional scenarios and increased scope of checking.
- Updates based on feedback from a diversity of field cases, increasing quality of both the checking of circuits and the reporting of information.
The previous release, v5.20, was a major update which included multi-core support for faster run times, and a significant change to the workflows for power states and floating node checks.
