For Mixed Power,
High Reliability Circuits

Slider

Full Chip, Transistor Level Reliability

Integrating circuit cores together in one chip exposes risks that can fly below the radar of conventional checking methods. After individual cores have been exhaustively simulated, there's still the question of reliability. This is an especially important topic in today's design flows for mixed power and low power.

Checking circuit reliability doesn't have to be difficult. A circuit engineer should be able to bring up a tool, with minimal setup, and get clear results. Tweak the circuit, fix an issue, and submit the updates. - All without waiting on the CAD team for help.

And simple to use doesn't mean simple minded. Checks must be smart enough to know about the ins and outs of real world circuits, automatically. Like novel level shifter topologies, ad-hoc domain isolation, safe vs unsafe power states, and other unexpected situations.

News

We're excited to announce the release of Insight Analyzer v4.9. This version brings a number of substantial updates, including:

  • Enhanced Conditional High Impedance detection for logic, analog, power management / domain crossing, and self-dependent loop cases.
  • Additional waiver storage formats.
  • Automatic recognition of valid one-hot controls, for increased rejection of false positives.
  • Enhanced topology searching and recognition of analog cases, further level shifter variations, etc.
  • Increased coverage of the many sources of unintended leakage: floats, mismatched levels, parasitic diodes, etc.
  • Expanded API commands for state based analysis.

Please see the full release notes here

New developments for leakage detection

Parasitic Leakage

  • Leakage through parasitic body diodes.
  • Bulk is not biased high enough (PMOS) or low enough (NMOS).
  • Long term reliability risk (device degradation over multiple cycles).
  • Short term reliability risk (latch up, damage).
  • Poor power performance (battery leakage).

Analog Gate Leakage

  • Leakage from power supply to ground, through MOSFET stacks.
  • Gate input floating, high impedance state.
  • Low reliability: Improper states, unreliable outcomes, etc.
  • High current drain.

Digital Gate Leakage

  • Category of power management / mismatch issues.
  • Input may be under driven, “missing level shifter”.
  • Input may be floating, high impedance state.
  • Low reliability: Improper states, unreliable outcomes, etc.
  • High current drain.