For Mixed Power,
High Reliability Circuits


Full Chip, Transistor Level Reliability

Integrating circuit cores together in one chip exposes risks that can fly below the radar of conventional checking methods. After individual cores have been exhaustively simulated, there's still the question of reliability. This is an especially important topic in today's design flows for mixed power and low power.

Checking circuit reliability doesn't have to be difficult. A circuit engineer should be able to bring up a tool, with minimal setup, and get clear results. Tweak the circuit, fix an issue, and submit the updates. - All without waiting on the CAD team for help.

And simple to use doesn't mean simple minded. Checks must be smart enough to know about the ins and outs of real world circuits, automatically. Like novel level shifter topologies, ad-hoc domain isolation, safe vs unsafe power states, and other unexpected situations.


We're excited to announce the release of Insight Analyzer v5.20.
This is a major update with new features and changes to the workflow, since the previous minor release of v5.01.

  • Multi-core support for significantly faster run times.
  • New "split" in workflow between "System Scan" and "Analog Sweeps" modes, which affects Power Connections and Float checks.
  • Major improvements to Power and State editing workflow, including the ability to edit boundary and isolation info in the GUI.
  • Making power state definitions more intuitive with changes to rail definitions and the meaning of "0V" compared to "off".
  • Changes to recognition, API, bug fixes, and other minor changes.
Please see the full release notes for more information.

See release notes for previous releases: v5.01, v5.0.

New developments for leakage detection


Parasitic Leakage

  • Leakage through parasitic body diodes.
  • Bulk is not biased high enough (PMOS) or low enough (NMOS).
  • Long term reliability risk (device degradation over multiple cycles).
  • Short term reliability risk (latch up, damage).
  • Poor power performance (battery leakage).

Analog Gate Leakage

  • Leakage from power supply to ground, through MOSFET stacks.
  • Gate input floating, high impedance state.
  • Low reliability: Improper states, unreliable outcomes, etc.
  • High current drain.

Digital Gate Leakage

  • Category of power management / mismatch issues.
  • Input may be under driven, “missing level shifter”.
  • Input may be floating, high impedance state.
  • Low reliability: Improper states, unreliable outcomes, etc.
  • High current drain.