For Mixed Power,
High Reliability Circuits

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Full Chip, Transistor Level Reliability

Integrating circuit cores together in one chip exposes risks that can fly below the radar of conventional checking methods. After individual cores have been exhaustively simulated, there's still the question of reliability. This is an especially important topic in today's design flows for mixed power and low power.

Checking circuit reliability doesn't have to be difficult. A circuit engineer should be able to bring up a tool, with minimal setup, and get clear results. Tweak the circuit, fix an issue, and submit the updates. - All without waiting on the CAD team for help.

And simple to use doesn't mean simple minded. Checks must be smart enough to know about the ins and outs of real world circuits, automatically. Like novel level shifter topologies, ad-hoc domain isolation, safe vs unsafe power states, and other unexpected situations.

News

We're excited to announce the release of Insight Analyzer v5.01.
This incremental update of Insight Analyzer has minor fixes and updates over prior version v5.00.

  • Changes to recognition of memory, latches, and NOR/XOR.
  • Many reports now provide Reference "R" numbers in in the Details view, corresponding to specific example reference files.
  • New "Diagnostic Trace" tool to show a debugging trace for a specific net or instance. It is accessed from the menu “Extensions > Utilities > Diagnostic Trace”.
  • The way that Analog Float checks handle analog switched diodes has been made more accurate.
  • Updates to various API commands.
  • Various bug fixes to license timeout, device wrappers, GUI, and more.
Please see the full release notes for more information.


See release notes for the previous major v5.0 release here.

New developments for leakage detection

parasitic-leakage.png

Parasitic Leakage

  • Leakage through parasitic body diodes.
  • Bulk is not biased high enough (PMOS) or low enough (NMOS).
  • Long term reliability risk (device degradation over multiple cycles).
  • Short term reliability risk (latch up, damage).
  • Poor power performance (battery leakage).
analog-gate-leakage.png

Analog Gate Leakage

  • Leakage from power supply to ground, through MOSFET stacks.
  • Gate input floating, high impedance state.
  • Low reliability: Improper states, unreliable outcomes, etc.
  • High current drain.
digital-gate-leakage.png

Digital Gate Leakage

  • Category of power management / mismatch issues.
  • Input may be under driven, “missing level shifter”.
  • Input may be floating, high impedance state.
  • Low reliability: Improper states, unreliable outcomes, etc.
  • High current drain.