Provides a technical overview of the methods of calculating and checking fanout of logic circuits, using Insight Analyzer.
Introduces a new mode of state-based validation, called Analog States. It closely resembles traditional UPF (Unified Power Format) tables, but adds new enhancements and overcomes the classic limitations of UPF.
Demonstrates how Insight Analyzer recognizes patterns in MOSFET level circuits, such as level shifters, memory bit cells, keepers, current mirrors, etc.
Describes how leakage between power domains is difficult to detect, and how the Insight Analyzer uses proprietary methods to find potential domain leakage issues.
Gives solutions to customizing the built-in Fanout checks with different threshold values for "clocked" nodes, without writing a custom check.