Analog Gate Leakage

Leakage in MOSFET stacks, caused by floating, high-impedance gate state.
This section covers cases that are generic, such as passgates, analog pinch-off, and others that are not CMOS drivers.

  • Amplifier floating output

    An amplifier drives to inverter input.

    • If the digital cut off is applied, the inverter input will be floating.
    • If the amplifier current is turned off, the inverter input will be floating.

    Insight Analyzer runs a complete scan of all possibilities on these nodes. In most cases, there will not be a possibility of float, and those cases will be safe.

    In this case, it is possible to make the inverter input float. Insight Analyzer reports this as a violation:

    Category Floating Nodes
    Violation “Conditional float”
    Details Given Inverter gate input “nt23”
    States of involved nodes

  • Current mirror slave

    A current mirror was used to gate a slave MOSFET in another stack.

    An input keeps the current mirror on. If the input is removed, the current mirror will collapse, and the slave MOSFET gate will begin to float.

    This circuit passed simulation and became a silicon failure.

    Insight Analyzer finds the key input, and enforces the correct handling of key input state. If the key input is in the proper state, a violation is prevented.

    Category Floating Nodes
    Violation “Conditional float”
    Details Given Victim float node “na0”
    States of involved nodes
    Key input “wpg” in high state

  • Loop startup problem

    A delay circuit has feedback to latch a “ready” state.

    The circuit passes simulation, and the silicon seems to function normally.

    However, there is no proper reset input. The feedback loop creates an unpredictable startup problem.

    In some cases, the loop is stuck with a floating internal node.

    Insight Analyzer reports this as a special case of self-dependency.

    Category Floating Nodes
    Violation “Conditional float”
    Loop + Logic
    Details Given Inverter gate input “tdel”
    States of involved nodes
    Key inputs leading to cause

  • Latch clocks, incorrect phase

    A latch cell uses external differential clock. In the upper cell, the clock inputs were connected to the same matching phase.

    The matching phase is incorrect, resulting in an internal floating node.

    While this is a CMOS circuit, the low level fault is found by enabling full analog checking in the Floating Nodes application.

    Insight Analyzer finds this problem of incorrect clock phase:

    Category Floating Nodes
    Violation “Conditional float” Logic
    Details Given Inverter gate input node
    States of involved nodes
    Key inputs leading to cause

  • Summary & Workflow: Analog Gate Leakage

    The cases in this section are generally considered “analog”, and power supply mixture is not involved.

    This form of checking is the most time consuming, as it is close to simulation. Generally, these checks should be run at the lower block level, not up at the higher integration layers.

    1. Floating Nodes. Thisistheprimarysetof checks for cases in this section. It should be run with “Analog scenarios” enabled.