Digital Gate Leakage

Leakage in MOSFET stacks, caused by floating, high-impedance or under driven gate state.
This section covers cases that are related to CMOS drivers, domain crossings, and isolation modes.

  • Boundary failure: External inputs off

    This example is an IP core with a leaking receiver input.

    • Boundary specs are known.
    • External signals have a known “off” state.
    • Good case is protected by NFET clamp.
    • Bad case: NFET clamp is gated by the wrong power state.

    Complete checking includes:

    1. Check isolation scheme (can be clamp type, NAND / NOR, isolation level shifter).
    2. Check isolation control master signal.
    3. Check control buffering and distribution (can be inverters, level shifters, logic gating if unconditional).
    4. Check power states: IO validity, driver rails, control buffer rails, receiver rails.

    From the above checks, the bottom case fails point (3). The isolation buffer is “off” when it is needed.

    Insight Analyzer finds this case in two check categories:

    Category Isolation Network
    Violation “Iso Ctrl Xing at Buffer” (broken chain of control)
    Details Given Iso control buffer instance
    Iso control master signal
    Rail names
    Power states: table & state
    Category Floating Nodes
    Violation “Conditional float”
    (control arrives from off buffer)
    Details Given Inverter gate input
    IO name
    Rail names
    Power states: table & state

  • Isolation control propagation failure

    Sometimes, the point of isolation is OK, but the propagation of control is broken.

    In this example, we have a control network, passing through different power supplies.

    • Good case is protected by NFET clamp. The control propagation is not affected by ‘off’ buffering.
    • In another case, the control propagation stops at a high output, powered by ‘off’ supply.

    What does Insight Analyzer tell us?

    Isolation NFET clamp design is fine but it is a violation in the Isolation Network checks.

    Category Isolation Network
    Violation “Iso Ctrl Xing at Buffer” Limited by less on domain (broken chain of control)
    Details Given Iso control buffer instance
    Iso control master signal
    Driver / Receiver rail names
    Iso control propagation states (polarity of isolation control tree )
    Power states: table & state

  • Bad isolation cell, not isolation!

    This faulty cell design passed simulation, and was heading for tape-out.

    Simulation had expected output value. However, there was a serious issue inside the cell: Level shifter did not have internal power cut or clamping.

    Faulty cell had internal leakage.

    What does Insight Analyzer tell us?

    The cell is not an isolation cell, hence, it is a violation in the float checks.

    Category Floating Nodes
    Violation “Missing isolation”
    Details Given Floating NMOS gate inputs
    On and off rail names
    Power states: table & state

  • Good isolation cell, bad controls

    Circuit designer used an isolation cell as a plain level shifter. He hard tied the enable, up near the top of circuit.

    Later, the system architecture changed. A new power mode was added.

    Circuit designer could see “isolation cell” in the “proper place”. He assumed it was OK.

    In the new power mode, the isolation cell began to float.

    While this is a valid isolation cell, Insight Analyzer detects the true circuit failure.

    Category Floating Nodes
    Violation “Faulty isolation”
    (VDD is not a valid control)
    Details Given Floating nodes inside the cell
    VDD false control name
    Rail names: on & off
    Power states: table & state

  • Power “on” is actually floating

    A level shifter is connected to valid power / ground on input side.

    One power mode has the “ground” lifted up to the value of the supply.

    When the ground is lifted, nodes inside the level shifter will float.

    The violation is based on known power states, reaching a cell that is not isolation.

    Category Power Connections
    Violation “Float, LS internal” (LevelShifter)
    Details Given LS input rails pinch together
    Rail names
    Power state: table & state

  • Summary: Digital Gate Leakage

    The cases in this section are generally considered “digital”, and often involve power supply mixture.

    These are essentially domain crossing situations. Generally, these checks should be run at higher integration layers.

    1. Floating Nodes. This is a primary set of checks for cases in this section. It should be run with “Cross-Domain Isolation” enabled. Power states should be defined, and I/O domains may be defined (UPF).
    2. Power Connections. This is the primary set of checks for cases of “missing level shifter”.
    3. Isolation Network. This is a secondary set of checks, aimed at the networks that control isolation. The network itself may be faulty, before reaching isolation.
    4. Domain Crossings. This is an optional audit report.
    5. Level Shifters. This is an optional audit report.

  • Workflow: Digital Gate Leakage